On-chip and inter-chip communications are realized by circuit devices called buses. A bus consists of parallel, aligned, similar wires that in most cases are on the same metal layer. Buses transmit units of information at a given fixed rate R (e.g., byte/sec). Some parallel buses are provided from parallel, capacitively-coupled transmission lines. The capacitive coupling introduces delay in the propagation of a signal from bus driver to bus receiver. Buses with capacitively-coupled lines have the property that the propagation time required for a signal depends upon the change (or transition) between the new data set to be transmitted on the lines and the last data set that was transmitted on the lines. Prior techniques estimate the delay associated with the capacitive coupling by modeling worst-case transitions. Typically, the rate R specified for such a bus is chosen to be sufficiently small to accommodate the delays associated with all the possible transitions.
To complicate matters further, the properties of the bus wires do not scale with technology in a favorable way. In modern technologies, in particular, deep sub-micron (DSM) technologies, there is increased capacitive coupling between the lines of buses due to the smaller distances between the lines as well as the higher aspect ratio (height/width) necessary to maintain a linear resistance of reasonable size.